module top(
    input clk,
    input rst_src,
    input rst_des,
    input flag    
    );
    
    wire ready;
    wire [3:0] data;
    wire valid;
    
    source src(.clk(clk),.rst(rst_src),.ready(ready),.flag(flag),.data(data),.valid(valid));
    dest dest(.clk(clk),.rst(rst_des),.ready(ready),.data(data),.valid(valid));
      
endmodule